1. Field of the Invention (Technical Field):
The present invention relates to packaging of highly reliable, high-speed complex electronics, and more particularly to a method and apparatus for reworking circuits using a micro-castellated interconnect board with its related electrical parts and affixing it to the circuitry.
2. Background Art
As electronic devices get smaller and smaller the prior art methods of part substitution and repair of circuitry create errors on existing hardware and become very problematic, if not entirely troublesome. Repair of circuitry and rewiring of devices on high-speed circuitry needs to be manufacturable and to a great extent electrically identical and meet environmental requirements of the product's end use. The present invention addresses a method for incorporating these changes to surface mounted electronics.
An existing prior art device or method uses a custom hybrid part, which internally incorporates the electrical wiring changes with mount die(s) containing the affected parts and provides environmental protection for the electronics. Such a custom part is very expensive, requires extensive lead-time and is not compliant to the volume allocated to the existing electronics. This method is not adequate for an individual revision as it is cost prohibitive. It can only be utilized for multiple or similar revisions to a large quantity of printed wiring boards (PWB's).
Another prior art method is to scrap existing product circuit cards, re-layout the electronics, and procure new printed wiring boards and components. Other methods include reworking the circuit card assembly, usually called “dead bugging” of components and “cut and jumpering” of circuitry relying on highly skilled operators and requiring the visual aid of a microscope to complete. Presently, the accepted practice for military electronics is defined by standards for “cut and jumpering” of traces.
Scrapping product and re-layout of circuitry is costly and often causes delays in build schedules. Manual rework is not exact, is prone to human error and adds additional expense due to the use of highly skilled labor. Additionally, some product still gets scrapped due to damage during repair and the rework is not precise and may introduce variability in electrical integrity.
State of the art approaches have been relatively successful until the current generation of smaller geometry, high-speed electronic parts. Smaller parts require higher skill and use of magnification aids. As parts get smaller, the manual repair and replacement of parts becomes harder and at some point impossible due to human limitations. Higher speeds require more exact electrical wiring lengths and electrical trace separation. Depending upon the extent of the change, current approaches utilize additional adhesive to adhere part and wires to the circuit card assembly.
A re-layout of the base circuit board can accomplish the same function, that of rewiring, accommodating part changes and providing high reliability, however this approach would be extremely expensive. Additionally, this method may introduce additional errors in re-layout of complex very high-density circuitry by rerouting of critical signals. Other devices, such as individual parts can accomplish one of the desired outcomes but not all three, wiring changes, part changes, and high reliability.
There are several prior art documents that disclose castellations and/or outer land grid pads however, they do not address any context of providing a durable interconnect containing the combination of substrate design/materials, pad geometries, and castellation matched to the parent printed wiring board. Additionally, the intent of utilizing existing parent printed wiring board circuitry and providing changed electrical functionality that is both manufacturable and low cost is not addressed in any of the prior art.
These prior art documents include U.S. Pat. No. 6,609,915 B2 which discloses a piece that only forms the interconnect between a multichip module and the parent printed wring board. The present invention performs that function as well as providing new circuitry and mounting of parts and addresses the durability of the interconnect.
U.S. Pat. No. 6,377,464 B1 is a device which may have castellations for termination, but does not address durability of the interconnect. In fact, the method described for constellating a part lacks features, which could provide the necessary durability, namely bottom pads.
U.S. Pat. No. 5,247,423 has ½ vias which form periphery castellations allowing leads, wires or solder filled springs, to be attached and provide the interconnect to the parent printed wiring board. The present invention is a durable leadless interconnect.
U.S. Pat. No. 5,069,626 is a molded plastic device, which is molded to allow plating of castellations, which have additional geometry attachment to the parent printed wiring board. While it mentions that the individual “castellations area able to flex (on a microscopic level)” and it allows that the molded material may be matched to the “second component” it does not address how the castellations really flex and if this would be of any benefit to the level of stresses induced due to thermal coefficient of expansion mismatch, not to mention differential heating and cooling. Unless there is major accommodation in the mounting structure, aka flexibility, the solder joint geometry is critical to sustaining the thermally induced strains to meet the necessary durability.
None of the prior art documents teach or disclose the combination of substrate design/materials, pad and castellation geometries, which allow the formation of a robust solder joint. Additionally, the prior art fails to disclose the utilization of existing parent printed wiring board circuitry and providing changed electrical functionality that is both manufacturable and low cost.